1. Field of the Invention
The present invention relates to a display device, and more particularly, to a liquid crystal display (LCD) panel of high resolution and a method for manufacturing the same.
2. Discussion of the Related Art
Rapid developments in the field of information communication have caused an increase in the demand for thin, lightweight and low cost display devices for viewing information. Industries that develop display devices (or, simply, displays) are responding to these needs by placing high emphasis on developing flat panel-type displays. Historically, the Cathode Ray Tube (CRT) has been widely used as a display device for televisions, computer monitors and the like, because CRT screens can display various colors having high brightness. However, the CRT cannot adequately satisfy present demands for display applications that require display devices with reduced volume and weight, portability, lower power consumption, large screen size, and high resolution. Because of such requirements, the display industry has started placing more emphasis on developing flat panel displays to replace the CRT. Over the years, flat panel displays have found wide use in monitors manufactured for computers, spacecraft, aircraft, etc.
Some examples of the types of flat panel displays currently in use include the liquid crystal display (LCD), the electroluminescent display (ELD), the field emission display (FED), and the plasma display panel (PDP). Some characteristics that are required of an ideal flat panel display include light weight, high luminance, high efficiency, high resolution, high speed response time, low driving voltage, low power consumption, low cost, and natural color reproduction.
Generally, a phosphor material on a surface of the CRT emits light based on an externally applied display timing signal and an externally applied data signal, which control the trace of an electron beam. On the other hand, in an LCD panel, the electric field applied to the liquid crystals is controlled so as to control each crystal's transmittivity of light.
Development and applications of thin film transistor (TFT)-based LCD displays having increased dimensions and increased resolution is in demand. To increase productivity during manufacture of such displays, it is desirable to continue efforts to simplify manufacturing process steps and to improve the yield.
It is noted that the pitch between two pads in an LCD panel is a parameter that can be optimized for realizing an LCD panel with high resolution. In other words, the realization of an LCD panel with high resolution depends on how much the pitch between two pads is decreased.
Some relevant constructional details of a related art LCD panel are explained hereinbelow with reference to FIGS. 1-3. FIG. 1 is a plane view illustrating architectural details of a related art LCD panel, and FIG. 2 is a sectional view of the LCD panel in FIG. 1 taken along line of I-I′ in FIG. 1. Referring to FIG. 1 and FIG. 2, the related art LCD panel includes two glass substrates divided into a cell region (C), a pad region (P), and a liquid crystal interposed between them. A plurality of gate lines G1, G2 . . . Gn are arranged to cross a plurality of data lines D1, D2 . . . Dn on a first glass substrate 1 in the cell region (C), thereby defining a plurality of pixel regions in a matrix form. A pixel electrode 3 is formed in each pixel region. A TFT (Thin Film Transistor) is formed at each crossing point between a gate line and a data line.
The pad region P includes a plurality of gate pads Gp1, Gp2 . . . , Gpn and a plurality of data pads Dp1, Dp2 . . . Dpn. The gate pads transmit a gate signal output from a gate driving circuit (not shown) to the gate lines G1, G2 . . . Gn; and the data pads transmit a data signal output from a data driving circuit (not shown) to the data lines D1, D2 . . . Dn.
Although not shown in FIGS. 1 and 2, a black matrix layer and a color filter layer for displaying colors R, G, and B are arranged on a second glass substrate of the cell region. The black matrix layer prevents light from being transmitted from a pixel electrode and a TFT. A common electrode is arranged above the color filter layer so as to apply a common voltage to each pixel electrode 3.
The data pads are now explained with reference to FIG. 2. As shown in FIG. 2, the data pads Dp1, Dp2, and Dp3 extend from respective data lines D1, D2, and D3 in the cell region C. The data pads Dp1, Dp2 and Dp3 are formed above the gate insulating film 2 on the first substrate 1 in the pad region P with a fixed distance between two of them. Thereafter, a transparent conductive film 6 electrically connected to each data pad Dp1, Dp2, and Dp3 through a passivation film 4 on the data pads Dp1, Dp2, and Dp3 is formed. The transparent conductive film 6 transmits a driving signal received from an external driving circuit (not shown) through TCP (Tape Carrier Package) or COF (Chip on Film) to each data line.
The distance between each data line D1, D2, and D3 is called a “pitch.” For example, in FIGS. 1 and 2, the pitch P′ is a distance from the center of line D1 to that of line D2. In a related art LCD panel, the pitch P′ is about 50 μm and the respective transparent conductive films 6 require a minimum distance “W” to be connected to a Tape Carrier Package (TCP), which electrically connects the transparent conductive films 6 to a driving circuit.
However, to obtain an LCD panel of high resolution, that is, an LCD panel with more than 200 Pixels Per Inch (PPI), the pitch P′ should be less than 50 μm (e.g., approximately 42 μm). Accordingly, with the configuration illustrated in FIGS. 1 and 2, an LCD panel of resolution more than 200 PPI may not be obtained.
Many methods to obtain a higher pitch among adjacent data pads are proposed. For example, a Double Bank structure separately arranges pads at both sides of an LCD panel. FIG. 3 is a plane view illustrating a related art LCD panel with double bank structure. In FIG. 3, the odd numbered data pads such as Dp1, Dp3, . . . , Dpn−1 are arranged at a lower portion (or at an upper portion) of an LCD panel and the even numbered data pads such as Dp2, Dp4 . . . , Dpn are arranged at an upper portion (or a lower portion) of the panel, thereby obtaining a pitch that is higher than that obtained with the Single Bank structure shown in FIG. 1. In the cell region of first substrate 1 in FIG. 3, a plurality of gate lines G1, G2 . . . Gn are formed to cross a plurality of data lines D1, D2 . . . Dn. Also, in the pad region of the substrate 1, data pads Dp1, Dp2, Dp3 . . . , Dpn−1, and Dpn on corresponding data lines are alternately arranged at an upper or a lower portion of the LCD panel as shown in FIG. 3.
However, a related art LCD panel has the following problems. First, the Single Bank structure (such as that shown in FIG. 1) can not obtain an LCD panel having a resolution more than 200 PPI, because a Single Bank structure places a limit on decreasing the pitch, which is a distance between adjacent data pads, since a minimum pad width is required for electrical contact with a driving circuit. Second, although the minimum width required for electrical contact with the driving circuit is obtained in the Double Bank structure in spite of a decreased pitch, a separate arrangement of data pads on both sides of the LCD panel is required. Such a Double Bank architecture thus complicates the module fabrication process and driving circuitry arrangement. Furthermore, the double bank structure makes fabrication of compact panels impossible and also increases the LCD panel production cost.